A conventional inverter circuit comprises a PMOS, first to third NMOSs, and first and second NPN transistors. In the inverter circuit, a drain, a source, and a gate of the PMOS are connected to a drain of the first NMOS, a power supply terminal, and an input terminal, respectively, and a drain, a source, and a gate of the second NMOS are connected to an output terminal, a drain of the third NMOS, and the input terminal, respectively. A base, a collector, and an emitter of the first NPN transistor are connected to a connecting point between the drains of the PMOS and the first NMOS, the power supply terminal, the output terminal, respectively, and a base, a collector, an emitter of the second NPN transistor are connected to a connecting point between the source of the second NMOS and the drain of the third MNOS, the output terminal, and ground, respectively. Further, a gate and a source of the first NMOS are connected to the input terminal and ground, respectively, and a gate and a source of the third NMOS are connected to the output terminal and ground, respectively. Thus, a CMOS inverter is structured, wherein charges which are accumulated at the base of the first NPN transistor are drawn therefrom to ground by the first NMOS, so that the first NPN transistor is turned off, when the PMOS is turned off and the second NMOS is turned on, while charges which are accumulated at the base of the second NPN transistor are drawn therefrom to ground by the third NMOS, so that the second NPN transistor is turned off, when the PMOS is turned on and the second NMOS is turned off.
However, the conventional inverter circuit has a disadvantage in that it does not operate with a high speed, because an input capacitance is large due to a multi-gate input structure, and plural transistors are vertically arranged. Further, the conventional inverter circuit has other disadvantages in that an occupied area is large, and a power dissipation is large, because the number of circuitry elements is increased. The same disadvantage occurs in three input NAND and NOR circuits which are expanded from the inverter circuit described above.